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    Ghoreishizadeh S, Haci D, Liu Y, Constandinou Tet al.,

    A 4-wire interface SoC for shared multi-implant power transfer and full-duplex communication

    , IEEE Latin American symposium on Circuits and Systems (LASCAS), Pages: 49-52

    This paper describes a novel system for recoveringpower and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. Thetarget application requires a singleChest Devicebe connectedto aBrain Implantconsisting of multiple identical optrodesthat record neural activity and provide closed loop opticalstimulation. The interface is integrated within each optrode SoCallowing full-duplex and fully-differential communication basedon Manchester encoding. The system features a head-to-chestuplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) superimposed on a power carrier.On-chip power management provides an unregulated 5 V DCsupply with up to 2.5 mA output current for stimulation, anda regulated 3.3 V with 60 dB PSRR for recording and logiccircuits. The circuit has been implemented in a 0.35μm CMOStechnology, occupying 1.4 mm2silicon area, and requiring a62.2μA average current consumption.

    Dávila-Montero S, Barsakcioglu DY, Jackson A, Constandinou TG, Mason AJet al., 2017,

    Real-time Clustering Algorithm that Adapts to Dynamic Changes in Neural Recordings

    , IEEE International Symposium on Circuits & Systems (ISCAS)

    This work presents a computationally efficient real-time adaptive clustering algorithm that recognizes and adapts to dynamic changes observed in neural recordings. The algorithm consists of an off-line training phase that determines initial cluster positions, and an on-line operation phase that continuously tracks drifts in clusters and periodically verifies acute changes in cluster composition. Analysis of chronic recordings from non-human primates shows that adaptive clustering achieves an improvement of 14% in classification accuracy and demonstrates an ability to recognize acute changes with 78% accuracy, with up to 29% computational efficiency compared to the state-of-the-art. The presented algorithm is suitable for long-term chronic monitoring of neural activity in various applications such as neuroscience research and control of neural prosthetics and assistive devices.

    Gao C, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017,

    On-chip ID Generation for Multi-node Implantable Devices using SA-PUF

    , IEEE International Symposium on Circuits & Systems (ISCAS)

    This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.

    Haci D, Liu Y, Constandinou TG, 2017,

    32-Channel Ultra-Low-Noise Arbitrary Signal Generation Platform for Biopotential Emulation

    , IEEE International Symposium on Circuits & Systems (ISCAS)

    This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.

    Luan S, Williams I, De-Carvalho F, Grand L, Jackson A, Quian Quiroga R, Constandinou TGet al., 2017,

    Standalone Headstage for Neural Recording with Real-Time Spike Sorting and Data Logging

    , BNA Festival of Neuroscience
    Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2017,

    A Charge-based Ultra-Low Power Continuous-Time ADC for Data Driven Neural Spike Processing

    , IEEE International Symposium on Circuits & Systems (ISCAS)

    The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75uW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4uW. The circuit has been implemented in a commercially available 0.35um CMOS technology with core occupying a footprint of 0.12

    Schultz SR, Copeland CS, Foust AJ, Quicke P, Schuck Ret al., 2017,

    Advances in Two-Photon Scanning and Scanless Microscopy Technologies for Functional Neural Circuit Imaging

    , PROCEEDINGS OF THE IEEE, Vol: 105, Pages: 139-157, ISSN: 0018-9219
    Troiani F, Nikolic K, Constandinou TG, 2017,

    Optical coherence tomography for detection of compound action potential in Xenopus Laevis sciatic nerve

    , SPIE/OSA European Conferences on Biomedical Optics (ECBO)
    Barsakcioglu DY, Constandinou TG, 2016,

    A 32-Channel MCU-based Feature Extraction and Classification for Scalable On-node Spike Sorting

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1310-1313, ISSN: 0271-4302
    Berditchevskaia A, Caze RD, Schultz SR, 2016,

    Performance in a GO/NOGO perceptual task reflects a balance between impulsive and instrumental components of behaviour

    , SCIENTIFIC REPORTS, Vol: 6, ISSN: 2045-2322
    Chen S, Augustine GJ, Chadderton P, 2016,

    The cerebellum linearly encodes whisker position during voluntary movement

    , ELIFE, Vol: 5, ISSN: 2050-084X
    Cheung K, Schultz SR, Luk W, 2016,

    NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

    Elia M, Leene LB, Constandinou TG, 2016,

    Continuous-Time Micropower Interface for Neural Recording Applications

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 534-537, ISSN: 0271-4302
    Evans BD, Jarvis S, Schultz SR, Nikolic Ket al., 2016,

    PyRhO: A Multiscale Optogenetics Simulation Platform

    Frehlick Z, Williams I, Constandinou TG, 2016,

    Improving Neural Spike Sorting Performance Using Template Enhancement

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 524-527

    This paper presents a novel method for improving the performance of template matching in neural spike sorting for similar shaped spikes, without increasing computational complexity. Mean templates for similar shaped spikes are enhanced to emphasise distinguishing features. Template optimisation is based on the variance of sample distributions. Improved spike sorting performance is demonstrated on simulated neural recordings with two and three neuron spike shapes. The method is designed for implementation on a Next Generation Neural Interface (NGNI) device at Imperial College London.

    Leene L, Constandinou TG, 2016,

    A 2.7uW/Mips, 0.88GOPS/mm^2 Distributed Processor for Implantable Brain Machine Interfaces

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 360-363

    This paper presents a scalable architecture in 0.18u m CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributedprocessor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7uW/MIPS with a total chip area of 1.37mm2. This configuration executes 1024 instructions on each core at 20MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.

    Liu Y, Pereira JL, Constandinou TG, 2016,

    Clockless Continuous-Time Neural Spike Sorting: Method, Implementation and Evaluation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 538-541, ISSN: 0271-4302
    Luan S, Liu Y, Williams I, Constandinou TGet al., 2016,

    An Event-Driven SoC for Neural Recording

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 404-407

    This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs)and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Eachchannel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35u m CMOS technology occupying a silicon area of 19.1mm^2 (0.3mm^2 gross per channel) and requiring 32uW/channel power consumption (AFE only).

    Nicolaou N, Constandinou TG, 2016,

    Phase-Amplitude Coupling during propofol-induced sedation: an exploratory approach

    , FENS Forum of Neuroscience, Publisher: FENS
    Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou TGet al., 2016,

    An optrode with built-in self-diagnostic and fracture sensor for cortical brain stimulation

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 392-395

    This paper proposes a self-diagnostic subsystem for a new generation of brain implants with active electronics. The primary objective of such probes is to deliver optical pulses to optogenetic tissue and record the subsequent activity, but lifetime is currently unknown. Our proposed circuits aim to increase the safety of implanting active electronic probes into human brain tissue. Therefore, prolonging the lifetime of the implant and reducing the risks to the patient. The self-diagnostic circuit will examine the optical emitter against any abnormality or malfunctioning. The fracture sensor examinesthe optrode against any rapture or insertion breakage. The optrode including our diagnostic subsystem and fracture sensor has been designed and successfully simulated at 350nm AMS technology node and sent for manufacture.

    Reichenbach CS, Braiman C, Schiff ND, Hudspeth AJ, Reichenbach Tet al., 2016,

    The Auditory-Brainstem Response to Continuous, Non-repetitive Speech Is Modulated by the Speech Envelope and Reflects Speech Processing

    Reynolds S, Copeland CS, Schultz SR, Dragotti PLet al., 2016,


    , IEEE 13th International Symposium on Biomedical Imaging (ISBI), Publisher: IEEE, Pages: 676-679, ISSN: 1945-7928
    Sollini J, Chadderton P, 2016,

    Comodulation Enhances Signal Detection via Priming of Auditory Cortical Circuits

    , JOURNAL OF NEUROSCIENCE, Vol: 36, Pages: 12299-12311, ISSN: 0270-6474
    Tang J, Jimenez SCA, Chakraborty S, Schultz SRet al., 2016,

    Visual Receptive Field Properties of Neurons in the Mouse Lateral Geniculate Nucleus

    , PLOS ONE, Vol: 11, ISSN: 1932-6203
    Troiani F, Nikolic K, Constandinou TG, 2016,

    Optical coherence tomography for detection of compound action potential in Xenopus Laevis sciatic nerve

    , Conference on Clinical and Translational Neurophotonics; Neural Imaging and Sensing; and Optogenetics and Optical Manipulation, Publisher: SPIE-INT SOC OPTICAL ENGINEERING, ISSN: 0277-786X
    Warren RL, Ramamoorthy S, Ciganovic N, Zhang Y, Wilson TM, Petrie T, Wang RK, Jacques SL, Reichenbach T, Nuttall AL, Fridberger Aet al., 2016,

    Minimal basilar membrane motion in low-frequency hearing

    Williams I, Rapeaux A, Liu Y, Luan S, Constandinou TGet al., 2016,

    A 32-Channel Bidirectional Neural/EMG Interface with on-Chip Spike Detection for Sensorimotor Feedback

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 528-531

    This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25V, user configurable amplitude (max. 315 uA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 uW per channel with programmable gain between 225 - 4725. Signals are10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.

    Yousif N, Fu RZ, Bourquin BA-E-E, Bhrugubanda V, Schultz SR, Seemungal BMet al., 2016,

    Dopamine Activation Preserves Visual Motion Perception Despite Noise Interference of Human V5/MT

    , JOURNAL OF NEUROSCIENCE, Vol: 36, Pages: 9303-9312, ISSN: 0270-6474
    Zhao H, Dehkhoda F, Ramezani R, Sokolov D, Constandinou TG, Liu Y, Degenaar Pet al., 2016,

    A CMOS-Based Neural Implantable Optrode for Optogenetic Stimulation and Electrical Recording

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 286-289

    This paper presents a novel integrated optrode for simultaneous optical stimulation and electrical recording for closed -loop optogenetic neuro-prosthetic applications. The design has been implemented in a commercially available 0.35μm CMOS process. The system includes circuits for controlling the optical stimulations; recording local field potentials (LFPs); and onboard diagnostics. The neural interface has two clusters of stimulation and recording sites. Each stimulation site has a bonding point for connecting a micro light emitting diode (μLED) to deliver light to the targeted area of brain tissue. Each recording site is designed to be post-processed with electrode materials to provide monitoring ofneural activity. On-chip diagnostic sensing has been included to provide real-time diagnostics for post-implantation and during normal operation.

    Cheung K, Schultz SR, Luk W, 2015,

    NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

    , Front Neurosci, Vol: 9, ISSN: 1662-4548

    NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

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