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    Leene L, Constandinou TG,

    A 0.5V Time-Domain Instrumentation Circuit with Clocked and Unclocked Operation

    , IEEE International Symposium on Circuits & Systems (ISCAS), Publisher: IEEE

    This paper presents a time-domain instrumentation circuit with exceptional noise efficiency directed at using nanometre CMOS for next generation neural interfaces. Current efforts to realize closed loop neuromodulation and high fidelity BMI prosthetics rely extensively on digital processing which isnot well integrated with conventional analogue instrumentation. The proposed time-domain topology employs a differential ring oscillator that is put into feedback using a chopper stabalized low noise transcondutor and capacitive feedback. This realization promises better digital integration by extensively using time encoded digital signals and seemlessly allows both clocked & unclocked behavior which is useful on-chip characterization and interfacing with synchronous systems. A 0.5V instrumentation system is implemented using a 65nm TSMC technology to realize a highly compact footprint that is 0.006 in size. Simulation results demonstrate an excess of 55dB dynamic range with 3.5 Vrms input referred noise for the given 810nW total system power budget corresponding to an NEF of 1.64.

    Dávila-Montero S, Barsakcioglu DY, Jackson A, Constandinou TG, Mason AJet al., 2017,

    Real-time Clustering Algorithm that Adapts to Dynamic Changes in Neural Recordings

    , IEEE International Symposium on Circuits & Systems (ISCAS)

    This work presents a computationally efficient real-time adaptive clustering algorithm that recognizes and adapts to dynamic changes observed in neural recordings. The algorithm consists of an off-line training phase that determines initial cluster positions, and an on-line operation phase that continuously tracks drifts in clusters and periodically verifies acute changes in cluster composition. Analysis of chronic recordings from non-human primates shows that adaptive clustering achieves an improvement of 14% in classification accuracy and demonstrates an ability to recognize acute changes with 78% accuracy, with up to 29% computational efficiency compared to the state-of-the-art. The presented algorithm is suitable for long-term chronic monitoring of neural activity in various applications such as neuroscience research and control of neural prosthetics and assistive devices.

    Gao C, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017,

    On-chip ID Generation for Multi-node Implantable Devices using SA-PUF

    , IEEE International Symposium on Circuits & Systems (ISCAS)

    This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.

    Guven O, Eftekhar A, Kindt W, Constandinou TGet al., 2017,

    Low-Power Real-Time ECG Baseline Wander Removal: Hardware Implementation

    , IEEE International Symposium on Circuits & Systems (ISCAS)

    This paper presents a hardware realisation of a novel ECG baseline drift removal that preserves the ECG signal integrity. The microcontroller implementation detects the fiducial markers of the ECG signal and the baseline wander estimation is achieved through a weighted piecewise linear interpolation. This estimated drift is then removed to recover a “clean” ECG signal without significantly distorting the ST segment. Experimental results using real data from the MIT-BIH Arrhythmia Database (recording 100 and 101) with added baseline wander (BWM1) from the MIT-BIH Noise Stress Database show an average root mean square error of 34.3uV (mean), 30.4u V (median) and 18.4uV (standard deviation) per heart beat.

    Haci D, Liu Y, Constandinou TG, 2017,

    32-Channel Ultra-Low-Noise Arbitrary Signal Generation Platform for Biopotential Emulation

    , IEEE International Symposium on Circuits & Systems (ISCAS)

    This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.

    Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2017,

    A Charge-based Ultra-Low Power Continuous-Time ADC for Data Driven Neural Spike Processing

    , IEEE International Symposium on Circuits & Systems (ISCAS)

    The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75uW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4uW. The circuit has been implemented in a commercially available 0.35um CMOS technology with core occupying a footprint of 0.12

    Troiani F, Nikolic K, Constandinou TG, 2017,

    Optical coherence tomography for detection of compound action potential in Xenopus Laevis sciatic nerve

    , SPIE/OSA European Conferences on Biomedical Optics (ECBO)
    Barsakcioglu DY, Constandinou TG, 2016,

    A 32-Channel MCU-based Feature Extraction and Classification for Scalable On-node Spike Sorting

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1310-1313, ISSN: 0271-4302
    De Marcellis A, Palange E, Faccio M, Nubile L, Stanchieri GDP, Petrucci S, Constandinou Tet al., 2016,

    A New Optical UWB Modulation Technique for 250Mbps Wireless Link in Implantable Biotelemetry Systems

    , 30th Eurosensors Conference, Publisher: ELSEVIER SCIENCE BV, Pages: 1676-1680, ISSN: 1877-7058
    De Marcellis A, Palange E, Nubile L, Faccio M, Di Patrizio Stanchieri G, Constandinou Tet al., 2016,

    A Pulsed Coding Technique Based on Optical UWB Modulation for High Data Rate Low Power Wireless Implantable Biotelemetry

    , Electronics, Vol: 5, Pages: 69-69
    Elia M, Leene LB, Constandinou TG, 2016,

    Continuous-Time Micropower Interface for Neural Recording Applications

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 534-537, ISSN: 0271-4302
    Frehlick Z, Williams I, Constandinou TG, 2016,

    Improving Neural Spike Sorting Performance Using Template Enhancement

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 524-527

    This paper presents a novel method for improving the performance of template matching in neural spike sorting for similar shaped spikes, without increasing computational complexity. Mean templates for similar shaped spikes are enhanced to emphasise distinguishing features. Template optimisation is based on the variance of sample distributions. Improved spike sorting performance is demonstrated on simulated neural recordings with two and three neuron spike shapes. The method is designed for implementation on a Next Generation Neural Interface (NGNI) device at Imperial College London.

    Lauteslager T, Tommer M, Kjelgard KG, Lande TS, Constandinou TGet al., 2016,

    Intracranial Heart Rate Detection Using UWB Radar

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 119-122

    Microwave imaging is a promising technique for noninvasive imaging of brain activity. A multistatic array of body coupled antennas and single chip pulsed ultra-wideband radars should be capable of detecting local changes in cerebral blood volume, a known indicator for neural activity. As an initialverification that small changes in the cerebrovascular system can indeed be measured inside the skull, we recorded the heart rate intracranially using a single radar module and two body coupled antennas. The obtained heart rate was found to correspond to ECG measurements. To confirm that the measured signal was indeed from within the skull, we performed simulations to predict the time-of-flight of radar pulses passing through differentanatomical structures of the head. Simulated time-of-flight through the brain corresponded to the measured delay of heart rate modulation in the radar signal. The detection of intracranial heart rate using microwave techniques has not previously been reported, and serves as a first proof that functional neuroimaging using radar could lie within reach.

    Leene L, Constandinou TG, 2016,

    A 2.7uW/Mips, 0.88GOPS/mm^2 Distributed Processor for Implantable Brain Machine Interfaces

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 360-363

    This paper presents a scalable architecture in 0.18u m CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributedprocessor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7uW/MIPS with a total chip area of 1.37mm2. This configuration executes 1024 instructions on each core at 20MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.

    Liu Y, Pereira JL, Constandinou TG, 2016,

    Clockless Continuous-Time Neural Spike Sorting: Method, Implementation and Evaluation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 538-541, ISSN: 0271-4302
    Luan S, Liu Y, Williams I, Constandinou TGet al., 2016,

    An Event-Driven SoC for Neural Recording

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 404-407

    This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs)and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Eachchannel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35u m CMOS technology occupying a silicon area of 19.1mm^2 (0.3mm^2 gross per channel) and requiring 32uW/channel power consumption (AFE only).

    Luan S, Williams I, de Carvalho F, Jackson A, Quian Quiroga R, Constandinou TGet al., 2016,

    Next Generation Neural Interfaces for low-power multichannel spike sorting

    , FENS Forum of Neuroscience, Publisher: FENS
    Nicolaou N, Constandinou TG, 2016,

    A Nonlinear Causality Estimator Based on Non-Parametric Multiplicative Regression

    Nicolaou N, Constandinou TG, 2016,

    Phase-Amplitude Coupling during propofol-induced sedation: an exploratory approach

    , FENS Forum of Neuroscience, Publisher: FENS
    Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou TGet al., 2016,

    An optrode with built-in self-diagnostic and fracture sensor for cortical brain stimulation

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 392-395

    This paper proposes a self-diagnostic subsystem for a new generation of brain implants with active electronics. The primary objective of such probes is to deliver optical pulses to optogenetic tissue and record the subsequent activity, but lifetime is currently unknown. Our proposed circuits aim to increase the safety of implanting active electronic probes into human brain tissue. Therefore, prolonging the lifetime of the implant and reducing the risks to the patient. The self-diagnostic circuit will examine the optical emitter against any abnormality or malfunctioning. The fracture sensor examinesthe optrode against any rapture or insertion breakage. The optrode including our diagnostic subsystem and fracture sensor has been designed and successfully simulated at 350nm AMS technology node and sent for manufacture.

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